Transmitting data at high speeds between a dynamic random access memory (DRAM) device and a memory controller requires careful design of input/output (I/O) drivers to ensure that signaling rates are maximized. The circuit components used in such drivers typically have greater oxide thicknesses than core devices, and thus have greater impedances. The higher impedances in turn can limit the maximum signaling rate of these I/O drivers. In addition, device mismatches, variations in process, voltage, and temperature of the I/O driver circuitry can also further limit maximum signaling rates.